The present invention relates generally to a new semiconductor chip carrier connections, where the chip carrier and the second level assembly are made by a surface mount technology. More particularly, the invention encompasses surface mount technologies, such as, Ball Grid Array (BGA), Column Grid Array (CGA), to name a few, where the surface mount technology comprises essentially of a non-solder metallic connection, such as, a copper connection. The present invention is also related to Column Grid Array structures and process thereof.
Semiconductor devices are becoming smaller and more dense with the evolution of new technology. However, increases in circuit density produces a corresponding increase in overall challenges in chip connections. Chip manufacturers are therefore challenged to improve their products by constant innovations. Whereas significant improvements have been made in the chip interconnection technology, however, they alone are not sufficient to overcome all the concerns.
An area of the prior art where the current major innovations have been taken place are in the use of various Pb-free solder alloys as a connection between a chip and a substrate, and between a substrate and the next level interconnection.
For example, U.S. Pat. No. 5,328,660 (Gonya) discloses a lead-free, high temperature, tin based multi-component solder, where the solder alloy contains 78.4 weight percent tin and the balance being silver, bismuth and indium.
Similarly, U.S. Pat. No. 5,411,703 (Gonya) is directed to a lead-free, based multi-component solder, where the high solidus temperature solder alloy contains between 93 and 94 weight percent tin and the balance being antimony, bismuth and copper.
Whereas, U.S. Pat. No. 5,733,501 (Takao) discloses a fatigue testing of lead-free solder alloy, where a copper lead is passed through a hole in a glass epoxy resin copper laminate board/substrate and soldered by a solder alloy.
U.S. Pat. No. 5,874,043 (Sarkhel) discloses another lead-free high tin based multi-component solder, where the solder alloy contains between 70.5 to 73.5 weight percent tin and the balance being silver and indium.
Another area of innovation are the column grid array (CGA) chip carriers which are finding an increase use in chip carrier technologies, particularly when the chip carriers are made of a ceramic material. The chip carrier is typically made of a ceramic material or an organic laminate material. A plurality of solder columns are attached to the I/O (input/output) pads of the chip carrier and the next level package in order to provide an electrical connection between the two. See for example, U.S. Pat. No. 5,324,892 (Granier), assigned to International Business Machines Corporation, Armonk, N.Y., USA, and the disclosure of which is incorporated herein by reference, which teaches a method of fabricating an electronic interconnection, using solder columns. The solder columns are made of solder that has a melting point greater than about 250xc2x0 C. The prefabricated solder columns are attached to a chip carrier by utilizing a solder that has a melting point of less than about 240xc2x0 C. These solder columns are fabricated independently and loaded into a furnace fixture which is then aligned to the carrier. The high temperature solder columns are attached by reflowing the low temperature solder alloy. However, as a person skilled in the art would know that a solder column, which typically has a small diameter, is very soft, and as a result during fabrication of the chip carrier module, the columns can be easily damaged or bent. This problem gets compounded, especially if it is at multiple locations on the I/O pad array. Typical solution would be costly rework. Additionally, during card assembly these column grid array modules can be subjected to handling damages. And, as the interconnection density increases the solder column diameter would have to be reduced. This reduction in solder column diameter of course will lower the flexural strength of these solder columns and
As one can see that the prior art uses a Pb-free solder system, but, none of them teach a non-solder metallic interconnection segment to connect a chip to a substrate or a substrate to a board. Similarly, they do not teach the use of a copper-core column array in combination with the use of high-melt and low-melt solder alloys for connecting such a copper column grid array to a chip carrier and an organic card. These high and low-melt solder alloys can be chosen from either Pb-containing or Pb-free solder alloys. Furthermore, this invention is directed to a column grid array types of structure which alleviate the problems of the prior art and enables the high volume manufacture of chip carriers with column grid array connections.
The invention is a novel method and a structure for a high density column grid array connections.
Therefore, one purpose of this invention is to provide a structure and a method that will provide a high density column grid array connections.
Another purpose of this invention is to provide a non-solder metallic interconnection.
Still another purpose of this invention is to provide a non-solder metallic interconnection between a chip carrier and an electronic component.
Yet another purpose of this invention is to provide a copper interconnection between a chip carrier and an electronic component.
Still yet another purpose of the invention is to provide a copper interconnection between a chip carrier and an electronic component using lead based attach solders, for example, 90/10 Pb/Sn for the substrate side and 37/63 Pb/Sn eutectic for the card side.
Yet another purpose of this invention is to provide a lead free solders, such as, tin/antimony for the substrate side and tin/silver/copper alloy for the card side, in order to provide a secure connection of the copper interconnection between the card and the substrate.
Therefore in one aspect this invention comprises a metallic electrical interconnect between a first pad on a first substrate and a second pad on a second substrate wherein said electrical interconnect is of a non-solder metallic material.
In another aspect this invention comprises a method of securing an interconnect to a substrate, wherein over at least fifty percent of said interconnect is of a non-solder metallic material, comprising the steps of:
(a) fluxing an end of said interconnect,
(b) placing said fluxed end of said interconnect on a pad with at least one solder on said substrate,
(c) raising temperature from room temperature to between about 100xc2x0 C. to about 300xc2x0 C., near said fluxed end and said pad, and after reflowing said solder, bringing said interconnect to room temperature, and thereby securing said interconnect to said substrate.
In yet another aspect this invention comprises a method of securing an interconnect to a printed circuit board, wherein over at least fifty percent of said interconnect is of a non-solder metallic material, comprising the steps of:
(a) fluxing an end of said interconnect,
(b) placing said fluxed end of said interconnect on a pad with at least one solder on said printed circuit board,
(c) raising temperature from room temperature to between about 100xc2x0 C. to about 300xc2x0 C., near said fluxed end and said pad, and after reflowing said solder, bringing said interconnect to room temperature, and thereby securing said interconnect to said printed circuit board.
In still another aspect this invention comprises a method of securing an interconnect to a first substrate and a second substrate, wherein said interconnect is of a non-solder metallic material, comprising the steps of:
(a) fluxing a first end of said interconnect,
(b) placing said first fluxed end of said interconnect on a first pad with at least one first solder on said first substrate,
(c) raising temperature from room temperature to between about 100xc2x0 C. to about 300xc2x0 C., near said fluxed end and said first pad, and after reflowing said first solder, bringing said interconnect to room temperature,
(d) fluxing a second end of said interconnect,
(e) placing said second fluxed end of said interconnect on a second pad with at least one second solder on said second substrate,
(f) raising temperature from room temperature to between about 100xc2x0 C. to about 300xc2x0 C., near said fluxed end and said second pad, and after reflowing said second solder, bringing said interconnect to room temperature, and thereby securing said interconnect to said first substrate and said second substrate.